The present invention relates to integrated circuit (IC) devices, and in particular, configurable addressing for multiple chips in a package.
In the field of integrated circuit (IC) devices, several semiconductor die (commonly referred to as xe2x80x9cchipsxe2x80x9d) can be combined into a single protective package. For some applications, a plurality of the chips put into a single package can be the same type, such as, for example, memory or logic. This allows for increased functional capacity using readily available chips.
For integrated circuit devices having multiple chips of the same type in one package, it may be desirable during operation to access a specific one of such chips within the package for inputting or retrieving data/information. With previously developed techniques, a specific chip is accessed using one or more chip select signals, which select the desired chip. Such previously developed techniques, however, can be problematic. A user of a multiple-chip integrated circuit device must generate the chip select signal, either by programming or hardwiring electronic components which interface with the integrated circuit device. Furthermore, provision must be made to keep track of which information/data is or should be input or retrieved from which chip in the device. Also, the functional elements (e.g., logic or memory) on the separate chips cannot be viewed as a uniform group of elements, which are accessible as a whole. Rather, the elements on a first chip must be considered and treated as a first group, the elements on a second chip must be considered and treated as a second group, and so on. This complicates the use of and interaction with the multiple-chip integrated circuit device.
The disadvantages and problems associated with previously developed schemes and techniques for accessing multiple chips of the same kind in a single package have been substantially reduced or eliminated using the present invention.
In accordance with an embodiment of the present invention, a first semiconductor chip is provided which is operable to be incorporated along with at least a second semiconductor chip of the same type into an integrated circuit device within a single package. The integrated circuit device has a common address path for the first and second semiconductor chips. The first semiconductor chip includes an option logic circuit operable to generate a configuration signal for causing an address decode circuit to respond to a predetermined range of addresses conveyed in the common address path of the integrated circuit device. The address decode circuit is in communication with the option logic circuit. The address decode circuit is operable to decode an address conveyed in the common address path of the integrated circuit device using the configuration signal and to generate a selection signal for selecting the first semiconductor chip if the address falls within the predetermined range of addresses.
In accordance with another embodiment of the present invention, a method is provided for configurable addressing of a first semiconductor chip incorporated along with at least a second semiconductor chip of the same type into an integrated circuit device within a single package. The integrated circuit device has a common address path for the first and second semiconductor chips. The method includes: generating a configuration signal for causing the first semiconductor chip to respond to a predetermined range of addresses conveyed in the common address path of the integrated circuit device; and generating a selection signal for selecting the first semiconductor chip if an address conveyed in the common address path of the integrated circuit device falls within the predetermined range of addresses.
In accordance with yet another embodiment of the present invention, an integrated circuit device having a common address path is provided. The integrated circuit device includes a multi-chip module substrate. A plurality of semiconductor chips of the same type are attached to the multi-chip module substrate. Each semiconductor chip comprises a respective configurable addressing circuit for causing the semiconductor chip to respond to a respective predetermined range of addresses, wherein each semiconductor chip is selected by an address conveyed in the common address path of the integrated circuit device if the address falls within the respective predetermined range of addresses for the semiconductor chip
In accordance with still another embodiment of the present invention, an integrated circuit device includes a multi-chip module substrate. A plurality of semiconductor chips of the same type are attached to the multi-chip module substrate. A common address path is provided for the plurality of semiconductor chips. Each semiconductor chip comprises a respective plurality of functional elements, each functional element separately addressable by a respective address. Each semiconductor chip also includes a respective configurable addressing circuit for causing the semiconductor chip to respond to any address within a respective predetermined range of addresses. This respective predetermined range of may comprise the respective addresses for each functional element of the semiconductor chip, wherein said any address within the respective predetermined range of addresses is conveyed in the common address path of the integrated circuit device.
In accordance with another embodiment of the present invention, an integrated circuit device includes a multi-chip module substrate. A plurality of semiconductor chips of the same type can be attached to the multi-chip module substrate. A common address path for the plurality of semiconductor chips is provided. Each semiconductor chip may comprise a respective plurality of functional elements and respective configurable addressing circuit. Each functional element can be separately addressable by a respective address. The respective configurable addressing circuits cause the semiconductor chip to respond to any address within a respective predetermined range of addresses. The respective predetermined range of addresses comprises the respective address for each functional element of the semiconductor chip, wherein said any address within the respective predetermined range of addresses is conveyed in the common address path of the integrated circuit device.
In accordance with still yet another embodiment of the present invention, a decode circuit is provided for a first semiconductor chip which is operable to be incorporated along with at least a second semiconductor chip of the same type into an integrated circuit device within a single package. The integrated circuit device has a common address path for the first and second semiconductor chips. The decode circuit is operable to generate a selection signal for selecting the first semiconductor chip if an address conveyed in the common address path falls within a predetermined range of addresses.
In accordance with yet another embodiment of the present invention, an option logic circuit is provided for a first semiconductor chip operable to be incorporated along with at least a second semiconductor chip of the same type into an integrated circuit device within a single package. The integrated circuit device has a common address path for the first and second semiconductor chips. The option logic circuit is operable to be configured so that the first semiconductor chip responds to a predetermined range of addresses conveyed in the common address path of the integrated circuit device. The option logic circuit is operable to generate a configuration signal for causing the first semiconductor chip to be selected if an address conveyed in the common address path falls within the predetermined range of addresses.
In accordance with yet another embodiment of the present invention, a first semiconductor chip is provided. The first semiconductor chip is operable to be incorporated along with at least a second semiconductor chip of the same type into an integrated circuit device within in a single package. The integrated circuit device has a common address path for the first and second semiconductor chips. The first semiconductor chip includes a configurable addressing circuit operable to be configured so that the first semiconductor chip responds to a predetermined range of addresses in the common address path of the integrated circuit device, to decode an address conveyed in the common address path of the integrated circuit device, and to generate a selection signal if the address conveyed in the common address path falls within the predetermined range of addresses.
In accordance with another embodiment of the present invention, a method is provided for configurable addressing of a first semiconductor chip incorporated along with at least a second semiconductor chip of the same type into an integrated circuit device within a single package. The integrated circuit device has a common address path for the first and second semiconductor chips. The method comprises: configuring the first semiconductor chip to respond to a predetermined range of addresses in the common address path of the integrated circuit device; decoding an address conveyed in the common address path of the integrated circuit device; and generating a selection signal if the address conveyed in the common address path falls within the predetermined range of addresses.
Important technical advantages of the present invention are readily apparent to one skilled in the art from the following figures, descriptions, and claims.